Flash memory device and flash memory system including the same

ABSTRACT

A flash memory device including: a memory cell array; a signal generator inputting a first data fetch signal and outputting a second data fetch signal; and an output buffer circuit configured to output data from the memory cell array in sync with rising and falling edges of the second data fetch signal, wherein second data fetch signal is output along with data output from the output buffer circuit.

CROSS-REFERENCE TO RELATED APPLICATIONS

This U.S. non-provisional patent application claims priority under 35U.S.C. §119 of Korean Patent Applications No. 10-2008-0017956 filed onFeb. 27, 2008, and No. 10-2008-0061767 filed on Jun. 27, 2008, theentire contents of which are incorporated herein by reference.

BACKGROUND

The present disclosure relates to semiconductor memory devices and, moreparticularly, to flash memory devices.

Flash memory devices that are used as nonvolatile memories areelectrically erasable and programmable read-only memories (EEPROMs) inwhich plural memory blocks are erased or written with data by a one-timeprogramming operation. A general EEPROM has the feature that a memoryblock is just erasable or programmable in a fixed time. This means thatthe flash memories operate more rapidly and effectively in reading andwriting data when systems employing them read and write data from andinto other memory areas at the same time. Flash memories or EEPROMs areusually structurally configured such that insulation films enclosingcharge storage elements used for storing data are inevitably worn outafter the specific number of operations.

Flash memories store information on their silicon chips even without apower supply being activated. In other words, flash memories are able toretain their information without power consumption even in the face of apower interruption to the chips thereof. Additionally, flash memoriesoffer resistance to physical impulses and a fast access times forreading. With those features, flash memories are generally used asstorage units in electronic apparatuses powered up by batteries.

SUMMARY OF THE INVENTION

Exemplary embodiments of the present invention are directed to a flashmemory device with a reduced number of pins, and a flash memory systemincluding the same.

Exemplary embodiments of the present invention are directed to a flashmemory device suitable for fast data transmission, and a flash memorysystem including the same.

An exemplary embodiment of the present invention provides a flash memorydevice including: a memory cell array; a signal generator inputting afirst data fetch signal and outputting a second data fetch signal; andan output buffer circuit configured to output data from the memory cellarray in sync with rising and falling edges of the second data fetchsignal. The second data fetch signal is output along with data outputfrom the output buffer circuit.

In an exemplar embodiment, the signal generator delays the first datafetch signal and outputs the delayed signal as the second data fetchsignal.

In an exemplary embodiment, the flash memory device further includes aninput buffer circuit configured to input data in sync with the firstdata fetch circuit.

According to an exemplary embodiment, the flash memory device furtherincludes: a control logic circuit; and a reading/programming circuitcontrolled by the control logic circuit, reading data from the memorycell array in a reading operation and programming data into the memorycell array in a programming operation.

In an exemplary embodiment, the control logic circuit activates thesignal generator to output the second data fetch signal in a data outputcycle.

According to an exemplary embodiment, the flash memory device furtherincludes: a control logic circuit configured to discriminate a datainput/output cycle into an address latch cycle, a command latch cycle,an input data latch cycle, or a data output cycle with reference to acombination of an address latch enabling signal and a command latchenabling signal.

In an exemplary embodiment, the first data fetch signal is toggled inthe address latch cycle, the command latch cycle, the input data latchcycle, and the data output cycle.

In an exemplary embodiment, the control logic circuit determines thedata input/output cycle as a serial access cycle if the address andcommand latch enabling signals are all set on high level.

An exemplary embodiment of the present invention provides a flash memorydevice including: a memory cell array; a control logic circuitconfigured to discriminate a data input/output cycle into an addresslatch cycle, a command latch cycle, an input data latch cycle, or a dataoutput cycle with reference to a combination of an address latchenabling signal and a command latch enabling signal; areading/programming circuit controlled by the control logic circuit,reading data from the memory cell array in a reading operation andprogramming data into the memory cell array in a programming operation;a signal generator delaying a first data fetch signal and outputting asecond data fetch signal if the data input/output cycle is determined asthe data output cycle; and an output buffer circuit sequentiallyoutputting data of the reading/programming circuit in sync with risingand falling edges of the second data fetch signal if the datainput/output cycle is determined as the data output cycle. The seconddata fetch signal is output to an external device along with data outputfrom the output buffer circuit.

In an exemplary embodiment, the flash memory device further includes aninput buffer circuit operating in sync with the first data fetch signaland interfacing data to be stored in the memory cell array.

According to an exemplary embodiment, the output buffer circuit isconfigured to interface data in sync with the second data fetch signalby an edge alignment mode and a double data rate mode.

An exemplary embodiment of the present invention provides a flash memorysystem including: a flash memory device; and a memory controllerconfigured to control the flash memory device. The flash memory devicegenerates a second data fetch signal from a first data fetch signalprovided from the memory controller in a reading operation and outputsread data to the memory controller in sync with the second data fetchsignal, wherein the second data fetch is transferred to the memorycontroller along with the read data.

In an exemplary embodiment, the flash memory device outputs data to thememory controller in sync with the second data fetch signal by an edgealignment mode and a double data rate mode.

In an exemplary embodiment, the flash memory system includes one of anSSD, a memory module, and a memory card.

According to an exemplary embodiment, the flash memory device isconfigured to discriminate a data input/output cycle into an addresslatch cycle, a command latch cycle, an input data latch cycle, or a dataoutput cycle with reference to a combination of an address latchenabling signal and a command latch enabling signal that are providedfrom the memory controller.

In an exemplary embodiment, the first data fetch signal is toggled inthe address latch cycle, the command latch cycle, the input data latchcycle, and the data output cycle.

According to an exemplary embodiment, the flash memory device determinesthe data input/output cycle as a data output cycle if the address andcommand latch enabling signals are all set on high level.

In an exemplary embodiment, the data output cycles includes a serialaccess cycle of a reading operation, a data output cycle of anidentification reading operation, and a data output cycle of a statereading operation.

According to exemplary embodiments of the present invention, it ispossible to transfer data at a high frequency, while reducing the numberof pins as well.

A further understanding of the nature and advantages of exemplaryembodiments of the present invention herein may be realized by referenceto the remaining portions of the specification and the attached figures.

BRIEF DESCRIPTION OF THE FIGURES

Exemplary embodiments of the present invention will be understood inmore detail from the following descriptions taken in conjunction withthe following figures, wherein like reference numerals refer to likeparts throughout the various figures unless otherwise specified. In thefigures:

FIG. 1 is a schematic block diagram of a flash memory system accordingto an exemplary embodiment of the present invention;

FIG. 2 shows a table summarizing modes used to discriminate data typesinput through input/output pins in the flash memory system according toan exemplary embodiment of the present invention;

FIGS. 3A through 3F are timing diagrams showing operations of the flashmemory device according to an exemplary embodiment of the presentinvention;

FIG. 4 is a schematic block diagram of a flash memory system accordingto an exemplary embodiment of the present invention;

FIG. 5 is a schematic block diagram of a flash memory device accordingto an exemplary embodiment of the present invention;

FIG. 6 is a block diagram illustrating the signal generator and outputbuffer circuit of FIG. 5 in accordance with an exemplary embodiment ofthe present invention;

FIG. 7 is a block diagram of the memory controller according to anexemplary embodiment of the present invention;

FIG. 8 is a timing diagram showing a reading operation of the flashmemory system according to an exemplary embodiment of the presentinvention;

FIG. 9 is a timing diagram showing a reading operation of the flashmemory system according to an exemplary embodiment of the presentinvention;

FIG. 10 is a block diagram illustrating an application with the flashmemory system to an SSD in accordance with an exemplary embodiment ofthe present invention;

FIG. 11 is a block diagram illustrating a channel structure operablewith the flash memory system according to an exemplary embodiment of thepresent invention;

FIG. 12 is a schematic block diagram of a memory system according to anexemplary embodiment of the present invention;

FIG. 13 is a flow chart illustrating an operation of the memory systemshown in FIG. 12 in accordance with an exemplary embodiment of thepresent invention;

FIG. 14 is a schematic block diagram of a computing system including theflash memory device and memory controller according to an exemplaryembodiment of the present invention; and

FIG. 15 is a block diagram of a memory system according to an exemplaryembodiment of the present invention.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

Exemplary embodiments of the present invention will be described below,involving a flash memory device as an example in illustrating structuraland operational features of the present invention.

The present invention may, however, be embodied in different forms andshould not be construed as limited to the exemplary embodiments setforth herein. Rather, these exemplary embodiments are provided so thatthis disclosure will be thorough and complete, and will fully convey thescope of the present invention to those skilled in the art. Likereference numerals refer to like elements throughout the accompanyingfigures.

Hereinafter, an exemplary embodiment of the present invention will bedescribed in conjunction with the accompanying drawings.

FIG. 1 is a schematic block diagram of a flash memory system accordingto an exemplary embodiment of the present invention.

Referring to FIG. 1, the flash memory device according to an exemplaryembodiment of the present invention is equipped with a plurality ofcontrol pins, for example, ALE, CLE, /CE, /RWE, R/BB, and the like andinput/output pins I/O0˜I/O7. In this exemplary embodiment, ALE denotesan address latch-enable signal, CLE denotes a command latch-enablesignal, and /CE denotes a chip selection signal. Although not shown inthe FIG. 1, it should be understood by those of ordinary skill in theart that the flash memory device is further comprised of power pins, andso forth. The /RWE pin is provided for receiving a signal transferredfrom a memory controller 100 to a flash memory device 200. The flashmemory device 200 fetches data, an address, or a command transferredfrom the memory controller 100 by means of a signal, hereinafterreferred to as ‘data fetch signal’, input through the /RWE pin.Additionally, the flash memory device 200 outputs data toward the memorycontroller 100 in response to the data fetch signal input through the.RWE pin. In an exemplary embodiment, the flash memory device 200outputs data in sync with a low-to-high or high-to-low transition of thedata fetch signal input through the /RWE pin. Otherwise, the flashmemory device 200 outputs data in sync respectively with low-to-high andhigh-to-low transitions of the data fetch signal input through the /RWEpin. In summary, the flash memory device 200 is able to output data in asingle data rate (SDR) or double data rate (DDR) mode. Also, the flashmemory device 200 accepts an address or command in sync with low-to-highand/or high-to-low transition(s) of the data fetch signal input throughthe /RWE pin.

As well known by those of ordinary skill in the art, a generic flashmemory device may include /RW and /WE pins (not shown in FIG. 1). Thememory controller 100 outputs a clock signal to the /RE pin (not shown)in order to fetch data (including data that has been read) from theflash memory device. The memory controller 100 outputs a clock signal tothe /WE pin (not shown) in order to transfer data including addresses,commands, and program data to the flash memory device. A generic flashmemory device uses a dual clocking scheme accompanying the IRE and /WEpins in order to transfer information such as data, addresses, andcommands. On the other hand, the flash memory system of an exemplaryembodiment of the present invention employs a unified data fetch schemeby only using just the /RWE pin. By using the unified data fetch scheme,it is possible to reduce the number of pins in the flash memory device200 and the memory controller 100. As the flash memory device 200 isconfigured in the command/address/data multiplexed I/O architecture andthe unified clocking scheme is applied to the flash memory system, thereis a need for discriminating whether data input/output through theinput/output pins are read data, addresses, program data, or commands.This discrimination can be accomplished in various ways, which will bedetailed hereinbelow.

FIG. 2 shows a table summarizing modes used to discriminate data typesinput through the input/output pins in the flash memory system accordingto an exemplary embodiment of the present invention.

Referring to FIG. 2, the flash memory system according to an exemplaryembodiment of the present invention operates to discriminate a data typeby way of a logical combination with the control signals ALE and CLEinput respectively through the ALE and CLE pins. For instance, when thecontrol signals ALE and CLE are conditioned in low and high levelsrespectively, data input through the input/output pins are regarded as acommand. That is, the flash memory device 200 determines a datainput/output cycle as a command latch cycle in response to a logicalcombination with the control signals ALE and CLE. During this operation,the flash memory device 200 accepts data, that is, a command, by meansof the data fetch signal input through the /RWE pin. When the controlsignals ALE and CLE are conditioned in high and low levels respectively,data input through the input/output pins are regarded as an address.That is, the flash memory device 200 determines a data input/outputcycle as an address latch cycle in response to a logical combinationwith the control signals ALE and CLE. During this operation, the flashmemory device 200 accepts data, that is, an address, in sync with thedata fetch signal input through the /RWE pin. When the control signalsALE and CLE are all at a low level, data input through the input/outputpins are regarded as program data. That is, the flash memory device 200determines a data input/output cycle as an input data latch cycle inresponse to a logical combination with the control signals ALE and CLE.This means that the flash memory device 200 accepts data in sync withthe data fetch signal input through the /RWE pin. When the controlsignals ALE and CLE are all at a high level, the flash memory device 200outputs data in sync with the data fetch signal /RWE. That is, the flashmemory device 200 determines a data input/output cycle as a data outputcycle in response to a logical combination of the control signals ALEand CLE. In this exemplary embodiment, the data output cycle includes aserial access cycle of a reading operation, a data output cycle of anidentification (ID) reading operation, a data output cycle of a statereading operation, and so on.

According to the flash memory system of an exemplary embodiment of thepresent invention, the flash memory device 200 discriminates datainput/output cycles by logical combinations of the control signals ALEand CLE. In a data input cycle, the flash memory device 200discriminates whether data input through the input/output pins areaddress, command, or program data with reference to a logicalcombination of the control signals ALE and CLE.

FIGS. 3A through 3F are timing diagrams showing operations of the flashmemory device according to an exemplary embodiment of the presentinvention.

The flash memory device 200 reads a logical combination of the controlsignals ALE and CLE transferred from the memory controller 100. When theinput control signals ALE and CLE have low and high levels respectively,the flash memory device 200 determines a data input/output cycle as acommand latch cycle. Thus, as shown in FIG. 3A, the flash memory device200 inputs data from the input/output pins as a command in sync with thedata fetch signal /RWE. If the control signals ALE and CLE have high andlow levels respectively, the flash memory device 200, as shown in FIG.3B, determines a data input/output cycle as an address latch cycle. Thismeans that the flash memory device 200 accepts data from theinput/output pins as an address in sync with the data fetch signal /RWE.If the control signals ALE and CLE are all set on a low level, the flashmemory device 200 determines a data input/output cycle as an input datalatch cycle. Thus, as shown in FIG. 3C, the flash memory device 200accepts data from the input/output pins as program data in sync with thedata fetch signal /RWE. If the control signals ALE and CLE are all setto a high level, the flash memory device 200 determines a datainput/output cycle as a serial access cycle (after read) that is a dataoutput cycle. Thus, as shown in FIG. 3D, the flash memory device 200sequentially outputs data by way of the input/output pins in sync withthe data fetch signal /RWE.

Differing from the timing sequence of FIG. 3D and referring to FIG. 3E,the flash memory device 200 is operable by sequentially outputting datathrough the input/output pins in sync with the data fetch signal /RWEunder the condition that the control signals ALE and CLE are set on alow level. On the other hand, as shown in FIG. 3F, the flash memorydevice 200 is able to sequentially output data through the input/outputpins in sync with the rising and falling edges of the data fetch signal/RWE.

Owing to the unified data fetch scheme and the discrimination mode ofdata input/output cycle in accordance with the control signals ALE andCLE, it is possible to reduce the numbers of pins in the memorycontroller and the flash memory device. Although the unified clockingscheme is applied to the flash memory system according to an exemplaryembodiment of the present invention, the modes shown in FIGS. 3A through3F may be helpful in smoothly transferring an address, a command, anddata during a reading, programming, or erasing operation.

As can be seen from the aforementioned, the flash memory systemaccording to an exemplary embodiment of the present invention easilyconducts an interfacing operation by a single one of the data fetchsignal /RWE instead of the two signals /RE and /WE, thereby reducing thenumber of pins. In this case, a data input/output cycle todata/address/command is determined in operation type by a logicalcombination of the control signals ALE and CLE. Differing from theaforementioned mode, it is possible to determine an operation type ofthe data input/output cycle to data/address/command by means of an inputcommand.

FIG. 4 is a schematic block diagram of a flash memory system accordingto an exemplary embodiment of the present invention.

Referring to FIG. 4, the flash memory system shown in FIG. 4 ispractically the same as that shown in FIG, 1, however, with thefollowing difference. A flash memory device 400 of FIG. 4 generates adata fetch signal DFC, hereinafter referred to as ‘second data fetchsignal’, by means of the signal /RWE, hereinafter referred to as ‘firstdata fetch signal’, during a data output cycle, for example, a serialaccess cycle, and outputs data to a memory controller 300 along with thesecond data fetch signal DFC. The flash memory device 400 outputs datato the memory controller 300 together with the second data fetch signalDFC in an edge alignment mode and the DDR (double data rate) mode. Thememory controller 300 fetches data from the flash memory device 400 inresponse to the second data fetch signal DFC. The memory controller 300safely fetches data from the flash memory device 400, regardless of aninterval (transfer length) between the memory controller 300 and theflash memory device 400. More specifically, a data transmission modeaccording to an exemplary embodiment of the present invention may beuseful for a memory structure, for example, solid state disk, memorymodule, memory card, and the like where a plurality of flash memorydevices are coupled to a single channel in parallel. This is becausesuch a memory structure is configured such that the flash memory devicesare distanced from the memory controller in different intervals, thatis, there are different transfer lengths. If the intervals from thememory controller are different from each other, it is reasonable toassume they cause gaps on data transmission times from the flash memorydevices to the memory controller. This means that there is a requirementfor securing a wider data fetch margin for the purpose of stablyfetching data from the flash memory devices. Such a data fetch marginmay act as a limitation on fast data transmission. In other words, itwould not be easy to accomplish fast data transmission in the structure,such as a solid state disk (SSD) or memory module, without using thedata fetch signal according to exemplary embodiments of the presentinvention. An exemplary embodiment of the present invention is born outof the need to consider a data fetch margin, because the data fetchsignal is transferred to the memory controller from the flash memorydevice. Because of that, the data transmission scheme of the flashmemory system according to an exemplary embodiment of the presentinvention may be useful for fast (or high frequency) data transmission.

As can be seen from the above description, the flash memory system shownin FIG. 4 may be advantageous in implementing fast data transmission bymeans of the second data fetch signal DFC at the same time with a smoothprogress of the interfacing operation by means of the first data fetchsignal /RWE.

FIG. 5 is a schematic block diagram of a flash memory device accordingto an exemplary embodiment of the present invention.

Referring to FIG. 5, the flash memory device 400 includes a memory cellarray 410 storing N-bit data, where N is 1 or an integer larger than 1.The memory cell array 410 includes memory cells arranged in rows andcolumns. Although not shown in FIG. 5, each memory cell may be formed ofa nonvolatile memory cell such as a floating-gate memory cell,charge-trap flash memory cell, or phase-change memory cell. A rowselector (X-selector) 420 is operated by a control logic circuit 450,for selecting a row of the memory cell array 410 in response to anaddress, for example, row address, input through an input buffer circuit480. As well known, a page buffer circuit 430 functions as a senseamplifier circuit or writing driver circuit controlled by the controllogic circuit 450. A column selector (Y-selector) 440 is operated by thecontrol logic circuit 450, for selecting columns, or page buffers of thepage buffer circuit 430, in a predetermined unit, for example, ×8, byresponding to an address, for example, a column address, input throughthe input buffer circuit 480.

Still referring to FIG. 5, the control logic circuit 450 is configuredto control an overall operation of the flash memory device 400. Morespecifically, the control logic circuit 450 operates to discriminate adata input/output cycle in response to a logical combination with thecontrol signals ALE and CLE. As aforementioned, when the control signalsALE and CLE are conditioned on low and high levels respectively, theflash memory device 400 determines a data input/output cycle as acommand latch cycle. When the control signals ALE and CLE areconditioned on high and low levels respectively, the flash memory device400 determines a data input/output cycle as an address latch cycle. Whenthe control signals ALE and CLE are both conditioned on the low level,the flash memory device 400 determines a data input/output cycle as aninput data latch cycle. When the control signals ALE and CLE are bothconditioned on the high level, the flash memory device 400 determines adata input/output cycle as a serial access cycle (or data output cycle).More specifically, the control logic circuit 450 operates to control asignal generator 460 in accordance with a result of the determination.

The signal generator 460 receives the first data fetch signal /RWE andgenerates internal signals under control of the control logic circuit450. For instance, in the address/command/input data latch cycle, thesignal generator 460 outputs an internal signal DIC to the input buffercircuit 480 by means of the first data fetch signal /RWE in response toa signal from the control logic circuit 450. In this exemplaryembodiment, the internal signal DIC may have the same waveform as thefirst data fetch signal /RWE. In the serial access cycle (or the dataoutput cycle), the signal generator 460 outputs the second data fetchsignal DFC to an output buffer circuit 470 by means of the first datafetch signal /RWE in response to the control logic circuit 450. At thesame time, the second data fetch signal DFC is provided to the memorycontroller 300 by way of a driver 490. It can be understood by those ofordinary skill in the art that the signal generator 460 additionallygenerates internal signals, which are necessary for the flash memorydevice 400, by means of the first data fetch signal /RWE. Exemplarily,the signal generator 460 supplies a clock signal to the column selector440 by means of the first data fetch signal /RWE during the inputdata/serial access cycle. As well known, the column selector 440sequentially generates column addresses in sync with a clock signal (notshown) provided from the signal generator 460.

The output buffer circuit 470 outputs data from the column selector 440to the input/output pins I/O in the edge alignment manner by respondingto the second data fetch signal DFC provided from the signal generator460. In other words, the output buffer circuit 470 operates in sync withthe second data fetch signal DFC, configured to interface data read fromthe memory cell array 410. Because the second data fetch signal DFC isgenerated by means of the first data fetch signal /RWE, it is necessaryto consider latency between the first and second data fetch signals /RWEand DFC. For example, the second data fetch signal DFC begins to begenerated after a predetermined time after a high-to-low transition ofthe first data fetch signal /RWE (refer to FIG. 8). The output buffercircuit 470 outputs data during low-to-high and high-to-low transitionperiods of the second data fetch signal DFC. That is, the output buffercircuit 470 outputs data using the DDR mode and the edge alignment modein sync with the second data fetch signal DFC. Otherwise, the outputbuffer circuit 470 is able to output data during a low level period orhigh level period (or a low-to-high transition period) of the seconddata fetch signal DFC. In other words, the output buffer circuit 470outputs data even using the SDR mode and the edge alignment mode in syncwith the second data fetch signal DFC.

The input buffer circuit 480 operates in response to a signal from thecontrol logic circuit 450, for receiving data as an address/command orprogram data in sync with the internal signal DIC That is, the inputbuffer circuit 480 operates in sync with the internal signal DIC, thatis, the first data fetch signal /RWE, being configured to interface datato be transferred to the memory cell array 410. For instance, during theaddress/command latch cycle, the input buffer circuit 480 receives datathrough the input/output pins I/C as an address/command in sync with theinternal signal DIC. An input address is provided to the row selector420 and the column selector 440 and an input command is provided to thecontrol logic circuit 450. During the data input cycle, the input buffercircuit 480 accepts data as program data through the input/output pinsI/O in sync with the internal signal DIC.

In this exemplary embodiment, the row selector 420, the page buffercircuit 430, and the column selector 440 are controlled by the controllogic circuit 450, forming a reading/programming circuit to read datafrom the memory cell array 410 in the reading operation and to programdata into the memory cell array 410 in the programming operation.

For the flash memory system shown in FIG. 1, the flash memory device 200may include a signal generator configured to output an internal signalto be provided to the output buffer circuit, which is generated by meansof the first data fetch signal /RWE instead of the second data fetchsignal DFC. In this case, the internal signal applied to the outputbuffer circuit 480 may not be output externally, that is, to the memorycontroller 450. Except for this feature, the flash memory device shownin FIG. 1 is practically the same as that shown in FIG. 5.

As seen from the above description, the flash memory device according toan exemplary embodiment of the present invention is organized todiscriminate the data input/output cycle with reference to a logicalcombination of the control signals ALE and CLE and to output the datafetch signal DFC together with data during the serial access cycle (orthe data output cycle).

FIG. 6 is a block diagram illustrating the signal generator 460 andoutput buffer circuit 470 of FIG. 5 in accordance with an exemplaryembodiment of the present invention.

Referring to FIG. 6, the signal generator 460 includes a buffer 461 anda delay unit 462. The buffer 461 operates to buffer the first data fetchsignal /RWE and outputs the buffered signal as the internal signal DIC.As aforementioned, the internal signal DIC is provided to the inputbuffer circuit 480. The delay unit 462 is activated by an enablingsignal EN that is provided from the control logic circuit 450, therebydelaying the output signal DIC of the buffer 461. A delayed version ofthe internal signal DIC is output as the second data fetch signal DFC.For example, if a data input/output cycle is determined as the dataoutput cycle, the delay unit 462 outputs the second data fetch signalDFC in response to the enabling signal EN.

Referring again to FIG. 6, the output buffer circuit 470 includes aserializer 471 and a driver 472. The serializer 471 receives a pair ofdata ED and OD from the column selector 440 shown in FIG. 5 andsequentially outputs the input data ED and OD in response to the seconddata fetch signal DFC from the signal generator 460. For instance, theserializer 471 receives the data ED in sync with a first edge, forexample, a high-to-low transition, and then outputs the data ED to thedriver 472. Additionally, the serializer 471 receives the data OD insync with a second edge, for example, low-to-high transition, and thenoutputs the data OD to the driver 472. In this exemplary embodiment, thenumber of data bits comprising each data (ED or OD) is set to correspondwith the number of the input/output lines.

FIG. 7 is a block diagram of memory controller such as shown at 100 inFIG. 1 according to an exemplary embodiment of the present invention.

Referring to FIG. 7, the memory controller 300 is comprised of a hostinterface 310, a state machine 320, a random access memory (RAM) 330, anerror correction circuit (ECC) 340, and a Rash interface 350. The hostinterface 310 is provided for an interfacing operation with a host, forexample, computer, portable terminal, and the like. The state machine320 is configured to control an overall operation of the memorycontroller 300. The state machine 320 may be formed of a processor. TheRAM 330 is used for temporarily storing data that is to be transferredto the flash memory device 400 or read from the flash memory device 400.The RAM 330 may also be used as a working memory of the state machine320. The RAM 330 is made up with a dynamic or static RAM. The ECC 340 isconfigured to generate error check and correction data from the datathat is to be transferred into the flash memory device 400, and todetect and correct errors of the data that is read from the flash memorydevice 400.

Continuing on with FIG. 7, the flash interface 350 is provided forperforming an interfacing operation with the flash memory device 400.The flash interface 350 generates the control signals ALE, CLE, and /CE,and the data fetch signal /RWE in response to the state machine 320. Inparticular, as aforementioned, the flash interface 350 generates theunified data fetch signal /RWE instead of the two signals /RE and /WE.The flash interface 350 transfers data (address, command, or programdata) through the input/output lines I/O in sync with the first datafetch signal /RWE. Additionally, the flash interface 350 receives datafrom the flash memory device 400. The flash interface 350 is organizedby including a clock generator 351, an input/output buffer 352, and aninput buffer 353. The clock generator 351 is configured to generate thefirst data fetch signal /RWE and the input buffer 353 is configured toreceive the second data fetch signal DFC. The input/output buffer 352operates in sync with the first data fetch signal /RWE during an outputcycle, and it operates in sync with the second data fetch signal DFCduring an input cycle.

As aforementioned, because the data fetch signal DFC is transferred tothe memory controller 300 from the flash memory device 400, there is noneed to consider a data fetch margin. For that reason, the datatransmission scheme of the flash memory system according to an exemplaryembodiment of the present invention is useful in implementing fast datatransmission.

FIG. 8 is a timing diagram showing the reading operation of the flashmemory system according to an exemplary embodiment of the presentinvention.

A command and an address are transferred to the flash memory device 400from the memory controller 300 by predetermined timings in the commandand address latch cycles described above relative to FIGS. 3A and 3B.Once the command and address are transferred to the flash memory device400, the reading operation begins. As a result of the reading operation,data of a selected row or page are stored in the page buffer circuit430. Afterward, the data are sequentially transferred to the memorycontroller 300 from the flash memory device 400 in a predetermined unit.More specifically, as shown in FIG. 7, the memory controller 300 setsthe control signals ALE and CLE all on high level. As the controlsignals ALE and CLE are all set to the high level, the flash memorydevice 400 shown in FIG. 5 determines a data input/output cycle as theserial access cycle. This means that the signal generator 460 of theflash memory device 400 generates the second data fetch signal DFC bymeans of the first data fetch signal /RWE. As illustrated in FIG. 8, inorder to output data in the edge alignment mode, a value of latencytDFCD should be predetermined between the first and second data fetchsignals /RWE and DFC. As the signal generator 460 provides the seconddata fetch signal DFC, the output buffer circuit 470 outputs datasequentially in sync with the second data fetch signal DFC by the edgealignment mode. During this operation, the memory controller 300receives data from the flash memory device 400 in sync with the seconddata fetch signal DFC.

As shown in FIG. 8, the second data fetch signal DFC is maintained on ahigh impedance state (high-Z) in the periods out of the serial accesscycle.

Under the condition that the control signals ALE and CLE are all set ona high level, data are output in sync with the second data fetch signalDFC. On the other hand, as shown in FIG. 9, it is also permissible toconfigure the flash memory device of an exemplary embodiment of thepresent invention to be capable of outputting data in sync with thesecond fetch signal DFC under the condition that the control signals ALEand CLE are all set on a low level.

The flash memory system according to an exemplary embodiment of thepresent invention is applicable to, for example, a memory module, asolid state drive (SSD), a memory card, or so forth. Referring to FIG.10 showing an application that the flash memory system according to anexemplary embodiment of the present invention is configured to be anSSD, the SSD is comprised of an SSD controller 500 and a plurality offlash memory devices 600_1˜600 _(—) m. Each of the flash memory devices600_1˜600 _(—) m is substantially the same as that shown in FIG. 5, soit will not be further described. The flash memory devices 600_1˜600_(—) m are electrically connected to the SSD controller 500 so as toshare the input/output lines, the first and second data fetch signals/RWE and DFC, and the control signals ALE and CLE. Furthermore, theplural flash memory devices 600_1˜600 _(—) m are electrically connectedto the SSD controller 500, so as to receive respective control signals/CE1˜CEm corresponding thereto.

As aforementioned, in the flash memory system shown in FIG. 10, as thedata fetch signal DFC is transferred to the SSD controller 500 from eachflash memory device, there is no need of considering a data fetchmargin. For that reason, the data transmission scheme of the SSD shownin FIG. 10 is advantageous for fast data transmission.

FIG. 11 is a block diagram illustrating a channel structure operablewith the flash memory system according to an exemplary embodiment of thepresent invention.

Referring to FIG. 11, a flash memory device of ×16 architecture can bemade up by connecting flash memory devices of ×8 architecture inparallel. According to this channel structure, it is possible to extendby two times the number of the flash memory devices and correspondinglyincrease the capacity of the flash memory system. It will be seen bythose of ordinary skill in the art that the channel structure shown inFIG. 11 is applicable to the SSD shown in FIG. 10. One of two chips, forexample, Chip 1, uses the input/output lines IO[7:0] while the otherchip (Chip 2) uses the other input/output lines IO[15:8]. In thisexemplary embodiment, all of the control signals, for example, /CE, ALE,CLE, R/BB, /RWE, and DFC, need to be shared by the two chips.Furthermore, the flash interface and the flash memory device areconfigured to employ the same scheme as described hereinabove withregard to FIGS. 5 and 7.

By providing a delay circuit to the memory controller in correspondencewith a transmission delay time between the flash memory device and thememory controller, it is possible to implement fast data transmissionwithout using a data fetch signal. In other words, it is possible tofetch data from the flash memory device by means of the signal /RWEdelayed through the delay circuit, after measuring a transmission delaytime between the flash memory device and the memory controller andprogramming the delay circuit in correspondence with the measuredtransmission delay time.

FIG. 12 is a schematic block diagram of a memory system according to anexemplary embodiment of the present invention.

Referring to FIG. 12, the memory system according to an exemplaryembodiment of the present invention includes a memory controller 700 anda flash memory device 800. The flash memory device 800 shown in FIG. 12is practically the same as that shown in FIG. 1 or 4, but different inthe following feature. The flash memory device 800 shown in FIG. 12 isoperable in the SDR mode where data is input and output in sync with arising or falling edge of the data fetch signal /RWE, and also operablein the DDR mode where data is input and output in sync with rising andfalling edges of the data fetch signal /RWE. Such functional modes areselected by a selection signal SDR/DDR. When the selection signalSDR/DDR indicates the SDR mode, the flash memory device 800 receivesdata in sync with a rising or falling edge of the data fetch signal/RWE. When the selection signal SDR/DDR indicates the DDR mode, theflash memory device 800 receives data in sync with rising and fallingedges of the data fetch signal /RWE.

To set the SDR and DDR modes, the flash memory device 800 may employ amode register set (MRS) circuit 801 for use instead of the selectionsignal SDR/DDR. The SDR and DDR modes are alternatively conducted bysetting the MRS circuit 801 in response to a command correspondingthereto. For instance, in changing the operation pattern from the SDRmode to the DDR mode, or from the DDR mode to the SDR mode, the MRScircuit 801 is set by the command corresponding to the DDR or SDR mode.Once the MRS circuit 801 is set to conduct the DDR or SDR mode, theflash memory device 800 operates to interface with the memory controller700 in the selected DDR or SDR mode.

Nevertheless, an address and a command of an operation mode type in theflash memory device 800 are basically introduced thereto in the SDRmode. It is also permissible, however, for an address and a command tobe input into the flash memory device 800 in the DDR mode.

In this exemplary embodiment, the flash memory device 800 operates inthe SDR mode as a default.

Furthermore, in this exemplary embodiment, the aforementioned modechange is conducted by the memory controller 700.

FIG. 13 is a flow chart illustrating an operation of the memory systemshown in FIG. 12 in accordance with an exemplary embodiment of thepresent invention. Hereinafter will be detailed the operation of thememory system shown in FIG. 12 in conjunction with the accompanyingfigures.

As described above, a default mode of the flash memory device 800 shownin FIG. 12 is set to the SDR mode. According to this condition, the IDreading operation is first conducted in the SDR mode (S100). Here, aswell known by those of ordinary skill in the art, the ID readingoperation is carried out to read information, such as maker code, devicecode, internal chip number, cell type, the number of pages programmed ata time, page size, block size, redundant area size, the least serialaccess, plan number, plan size, and so on.

Next, the operation mode is selectively changed (S200). For instance, ifit is still desired to maintain the SDR mode, which is the default mode,in the flash memory device 800 even after the ID reading operation, theprocess for changing the operation mode will be skipped over. Otherwise,if there is a need to turn the operation mode of the flash memory device800 from the SDR to the DDR as the default mode after the ID readingoperation, the flash memory device 800 is converted in operation mode bymeans of one of the aforementioned ways, that is, the selection signalSDR/DR or the MS circuit 801 (S200). Then, a required operation of theflash memory device 800 is conducted in the SDR or DDR mode that hasbeen established (S300).

In an exemplary embodiment, even in the case of maintaining the flashmemory device 800 on the SDR mode as the default mode, the procedure forsetting the SDR mode may be carried out by the aforementioned way, thatis, by the MRS circuit 801 or the selection signal SDR/DDR.

Flash memory devices are kinds of nonvolatile memories capable ofkeeping data stored therein even without a power supply. With a rapidincrease of using mobile apparatuses such as cellular phones, personaldigital assistants (PDA), digital cameras, portable gaming consoles, andMP3, the flash memory devices are widely employed as code storage, aswell as data storage. The flash memory devices may be also utilized inhome applications such as high-definition televisions, digital versatiledisks (DVDs), routers, and global positioning systems (GPSs). Aschematic structure of a computing system including the flash memorydevice and memory controller according to the present invention isillustrated in FIG. 14. The computing system according to an exemplaryembodiment of the present invention is organized to include amicroprocessor 2100, a user interface 2200, a modem 2600 such as abaseband chipset, a memory controller 2400, and a flash memory device2500, all of which are electrically connected to a bus 2001. The flashmemory device 2500 may be configured substantially the same as thatshown in FIG. 1 or 4. The memory controller 2400 may be configuredsubstantially the same as that shown in FIG. 1 or 7 In the flash memorydevice 2500, N-bit data (N is a positive integer) that is processed oris to be processed by the microprocessor 2100 may be stored through thememory controller 2400. If the computing system shown in FIG. 14 is akind of mobile apparatus, it may be flier comprised of a battery 2300for supplying power thereto. Although not shown in FIG. 14, thecomputing system may be further equipped with an application chipset, acamera image processor, for example, a complementarymetal-oxide-semiconductor (CMOS) image sensor; that is, a CIS, a mobileDRAM, and so forth. The memory controller 2400 and the flash memorydevice 2500, for example, may constitute an SSD using nonvolatilememories.

FIG. 15 is a block diagram of a memory system according to an exemplaryembodiment of the present invention.

The system shown in FIG. 15 denotes a portable apparatus 4000. Theportable apparatus 4000 may be an MP3 player, a video player, acombination video and audio player, or so on. As shown in FIG. 15, theportable apparatus 4000 includes a memory 4640 and a memory controller4650 that are practically the same as those shown FIG. 1 and/or FIG. 12.The portable apparatus 4000 may further include an encoder and decoder4610, presentation components 4620, and an interface 4630.

Data (video, audio, and the like) processed by the encoder and decoder(EDC) 4610 can be input to the memory 4640, through the memorycontroller 4650, and output from the memory 4640. As illustrated bydotted lines in FIG. 15, data can be input directly into the memory 4640from the EDC 4610 and/or output directly into the EDC 4610 from thememory 4640.

The EDC 4610 is able to encode data in order to store the data into thememory 4640. For instance, the EDC 4610 is also able to conduct an MP3encoding operation with audio data in order to store the data in thememory 4640. In another operation, the EDC 4610 is able to conduct anMPEG encoding operation, for example, MPEG2, MPEG4, and the like, withvideo data in order to the data in the memory 4640. Additionally, theEDC 4610 may include pluralities of encoders for encoding data of othertypes in accordance with other data formats. For example, the EDC 4610may include an MP3 encoder for audio data and an MPEG encoder for videodata.

The EDC 4610 is able to decode an output of the memory 4640. Forinstance, the EDC 4610 is able to conduct an MP3 decoding operation withaudio data output from the memory 4640. In another operation, the EDC4610 is able to conduct an MPEG decoding operation, for example, MPEG2,MPEG4, and the like, with video data output from the memory 4640.Furthermore, the EDC 4610 may include pluralities of decoders fordecoding data of other types in accordance with other data formats. Forinstance, the EDC 4610 may include an MP3 decoder for audio data and anMPEG decoder for video data.

It can be also understood that the EDC 4610 may include decoders only.For example, previously encoded data can be received by the EDC 4610 andpassed through the memory controller 4650 and/or the memory 4640.

The EDC 4610 is able to receive data for encoding by way of theinterface 4630 or to receive previously encoded data. The interface 4630may be in accord with a known standard, for example, firmware, USB, andthe like. The interface 4630 may further include more than one interfaceunit. For instance, the interface 4630 may include a firmware interface,a USB interface, and so on. Data from the memory 4640 may even be outputby way of the interface 4630.

The presentation components 4620 are able to display data output fromthe memory and/or decoded by the EDC 4610. For instance, thepresentation components 4620 may include a speaker jack for outputtingaudio data, a display screen for outputting video data, and so on.

The flash memory and/or the memory controller according to exemplaryembodiments of the present invention can be mounted on theaforementioned system or apparatus by way of various types of packages.For instance, the flash memory and/or the memory controller may beplaced thereon by any package type, for example, Package-on-Package(PoP), Ball Grid Arrays (BGAs), Chip Scale Packages (CSPs), PlasticLeaded Chip Carrier (PLCC), Plastic Dual In-line Package (PDIP), Die inWaffle Pack, Die in Wafer Form, Chip-On-Board (COB), CERamic DualIn-line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), ThinQuad Flat Pack (TQFP), Small Outline (SOIC), Shrink Small OutlinePackage (SSOP), Thin Small Outline (TSOP), Thin Quad Flat Pack (TQFP),System In Package (SIP), Multi-Chip Package (MCP), Wafer-levelFabricated Package (WFP), Wafer-level Processed Stack Package (WSP), orWafer-level Processed Package (WSP).

The above-disclosed subject matter is to be considered illustrative, andnot restrictive, and the appended claims are intended to cover all suchmodifications, enhancements, and other exemplary embodiments, which fallwithin the true spirit and scope of the present invention. Thus, to themaximum extent allowed by law, the scope of the present invention is tobe determined by the broadest permissible interpretation of thefollowing claims and their equivalents, and shall not be restricted orlimited by the foregoing detailed description.

1. A flash memory device comprising: a memory cell array; a signalgenerator receiving a first data fetch signal and outputting a seconddata fetch signal; and an output buffer circuit configured to outputdata from the memory cell array in sync with rising and falling edges ofthe second data fetch signal, wherein the second data fetch signal isoutput along with data output from the output buffer circuit.
 2. Theflash memory device of claim 1, wherein the signal generator delays thefirst data fetch signal and outputs the delayed first data fetch signalas the second data fetch signal.
 3. The flash memory device of claim 1,further comprising: an input buffer circuit configured to input data insync with the first data fetch circuit.
 4. The flash memory device ofclaim 1, further comprising: a control logic circuit; and areading/programming circuit controlled by the control logic circuit,reading data from the memory cell array in a reading operation andprogramming data into the memory cell array in a programming operation.5. The flash memory device of claim 4, wherein the control logic circuitactivates the signal generator to output the second data fetch signal ina data output cycle.
 6. The flash memory device of claim 1, furthercomprising: a control logic circuit configured to discriminate a datainput/output cycle into one of an address latch cycle, a command latchcycle, an input data latch cycle, and a data output cycle with referenceto a combination of an address latch enabling signal and a command latchenabling signal.
 7. The flash memory device of claim 6, wherein thefirst data fetch signal is toggled in the address latch cycle, thecommand latch cycle, the input data latch cycle, and the data outputcycle.
 8. The flash memory device of claim 6, wherein the control logiccircuit determines the data input/output cycle as a serial access cycleif the address and command latch enabling signals are both set on a highlevel.
 9. The flash memory device of claim 1, wherein a single data ratemode is set as a default mode.
 10. The flash memory device of claim 9,wherein an identification reading operation is conducted in the singledata rate mode.
 11. The flash memory device of claim 10, wherein thedefault mode is selectively changed by a selection signal or commandafter the identification reading operation.
 12. A flash memory devicecomprising: a memory cell array; a control logic circuit configured todiscriminate a data input/output cycle into one of an address latchcycle, a command latch cycle, an input data latch cycle, and a dataoutput cycle with reference to a combination of an address latchenabling signal and a command latch enabling signal; areading/programming circuit controlled by the control logic circuit,reading data from the memory cell array in a reading operation andprogramming data into the memory cell array in a programming operation;a signal generator delaying a first data fetch signal and outputting asecond data fetch signal if the data input/output cycle is determined asthe data output cycle; and an output buffer circuit sequentiallyoutputting data of the reading/programming circuit in sync with risingand falling edges of the second data fetch signal if the datainput/output cycle is determined as the data output cycle, wherein thesecond data fetch signal is output externally along with data outputfrom the output buffer circuit.
 13. The flash memory device of claim 12,further comprising: an input buffer circuit operating in sync with thefirst data fetch signal and interfacing data to be stored in the memorycell array.
 14. The flash memory device of claim 12, wherein the outputbuffer circuit is configured to interface data in sync with the seconddata fetch signal by an edge alignment mode and a double data rate mode15. A flash memory system comprising: a flash memory device; and amemory controller configured to control the flash memory device, whereinthe flash memory device generates a second data fetch signal from afirst data fetch signal provided from the memory controller in a readingoperation and outputs read data to the memory controller in sync withthe second data fetch signal, wherein the second data fetch signal istransferred to the memory controller along with the read data.
 16. Theflash memory system of claim 15, wherein the flash memory device outputsdata to the memory controller in sync with the second data fetch signalby an edge alignment mode and a double data rate mode.
 17. The flashmemory system of claim 15, which includes one of solid state drive(SSD), a memory module, and a memory card.
 18. The flash memory systemof claim 15, wherein the flash memory device is configured todiscriminate a data input/output cycle into one of an address latchcycle, a command latch cycle, an input data latch cycle, and a dataoutput cycle with reference to a combination of an address latchenabling signal and a command latch enabling signal which are providedfrom the memory controller.
 19. The flash memory system of claim 18,wherein the flash memory device determines the data input/output cycleas a data output cycle if the address and command latch enabling signalsare all set on high level.
 20. The flash memory system of claim 18,wherein the data output cycles includes a serial access cycle of areading operation, a data output cycle of an identification readingoperation, and a data output cycle of a state reading operation.